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DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Reading from PIO
When reading from PIOs, as shown in Figure 23, the sampling is triggered by the same edge that the master uses
to clock in (read) the last data (LS) bit of the preceding byte, which may be PIO data or SRAM data. To be correctly
assessed, the PIO state must not changed during the t PS and t PH interval. The SO state is valid t V after the falling
edge of SCL. When reading from address 126h, the PIO state appearing first on SO is that of PIO7. With every
falling edge on SCK the next PIO state appears on SO. On the rising SCK edge after the state of PIO0 is shifted
out to SO, the PIOs of address 127h are sampled. Reading from address 127 first results in four 0-bits followed by
the state of PIO11 to PIO8. If the READ instruction is issued with starting address 126h, the DS28DG02 enters a
loop in which both groups of PIOs are read alternating between PIO0:7 and PIO8:11. This way the fastest PIO
sampling rate is f CLK / 16.
Figure 23. PIO Read-Access Timing
SCK
On this edge the master
This edge shifts the MS
reads the LS bit of the
previous PIO data byte.
PIOn
SPI Communication—Legend
Sampling
t PS
t PH
bit of the just sampled
PIO state to SO.
SYMBOL
SEL
DSEL
WREN
WRDI
WRSR
RFSH
DESCRIPTION
Falling Edge on CSZ
Rising Edge on CSZ
Write Enable Instruction
Write Disable Instruction
Write Status Register Instruction
Refresh Instruction
SYMBOL
WRITEL
WRITEH
READL
READH
<byte>
DESCRIPTION
Write Instruction with A8 = 0
Write Instruction with A8 = 1
Read Instruction with A8 = 0
Read Instruction with A8 = 1
Transfer of 1 Byte
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